1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a method of fabricating a liquid crystal display that includes a gate insulating film having different thickness in accordance with position, and a liquid crystal display having a gate insulting film having different thickness in accordance with position thereof.
2. Discussion of the Related Art
Generally, liquid crystal displays (hereinafter, referred to as LCD) control the light transmittance of liquid crystal cells in accordance with video signals, thereby displaying pictures corresponding to the video signals on a liquid crystal display panel where the liquid crystal cells are arranged in a matrix. In this case, a thin film transistor (hereinafter, referred to as TFT) is typically used as a switching device for the liquid crystal cells.
In such as a thin film transistor, a semiconductor layer is made from amorphous silicon or polycrystalline silicon. An amorphous LCD has an advantage in that it has relatively better uniformity and stable property, but also has a disadvantage in that pixel density is difficult to improve because the charge mobility of amorphous silicon is low. Differently from this, a polycrystalline LCD has an advantage in that the charge mobility of crystalline silicon is high, so that pixel density may be increased. Further, drive circuits requiring relatively rapid response time are mounted on a liquid crystal display panel to reduce a fabricating cost.
Such a polycrystalline LCD includes a liquid crystal display panel where liquid crystal cells are arranged in a matrix, and a drive circuit to drive the liquid crystal display panel. The liquid crystal display panel includes a picture display part having red, green and blue pixels formed at each intersection area of gate lines and data lines. Each of the red, green and blue pixels is comprised of one thin film transistor and one liquid crystal cell. The liquid crystal display panel is provided with a pixel electrode and a common electrode to apply electric field to each liquid crystal cell. Each pixel electrode is connected to any one of the data lines through source and drain terminals of the TFT, the switching device. A gate terminal of the TFT is connected any one of the gate lines that apply pixel voltage signals to the pixel electrodes of one line at a time. The drive circuit includes a gate driver to drive the gate lines and a data driver to drive data lines. The gate driver sequentially applies scan signals to the gate lines, thereby sequentially driving the liquid crystal cells of one line on the liquid crystal display at a time. The data driver supplies video signals to each data line whenever the gate signal is applied to any one of the gate lines. And the liquid crystal display further includes multiplexors connected between the data driver and the data lines. A plurality of switch devices included in the multiplexor are sequentially turned on for each horizontal period, thereby sequentially supplying the video signals through data input line from the data driver to the data lines. The multiplexors are formed within the liquid crystal display panel together with the picture display part.
Referring to FIG. 1, each switch device SW included in the multiplexor MUX has the same configuration as the thin film transistor TP of the picture display part.
Each switch device includes an active layer 14 formed on a lower substrate 2 with a buffer film 4 therebetween, a gate electrode 6 formed to overlap an active layer 14 with a gate insulating film 12 therebetween, and a source electrode 8 and a drain electrode 10 formed to be insulated from the gate electrode 6 with a go-between insulating film 16 therebetween. Herein, the source electrode 8 and the drain electrode 10 are connected to the active layer 14 through a source contact hole 20S and a drain contact hole 20D penetrating the go-between insulating film 16 and the gate insulating film 12. The protective film 18 protects the switch devices SW.
The thin film transistor TP includes an active layer 44 formed on the lower substrate 2 with the buffer film 4 therebetween, a gate electrode 36 formed to overlap the active layer 44 with the gate insulating film 12 therebetween, and a source electrode 38 and a drain electrode 40 formed to be insulated from the gate electrode 36 with the go-between insulating film 36 therebetween. Herein, the source electrode 38 and the drain electrode 40 are connected to the active layer 44 through a source contact hole 50S and a drain contact hole 50D penetrating the go-between insulating film 16 and the gate insulating film 12. The protective film 18 protects the thin film transistor TP. The drain electrode 40 of the thin film transistor TP is electrically connected to a pixel electrode 22 through a pixel contact hole 24 penetrating the protective film 18.
FIGS. 2A to 2H are sectional diagrams representing a fabricating method of a lower substrate provided with switch devices and thin film transistors shown in FIG. 1.
Firstly, the buffer film 4 of insulating material, such as SiO2, is deposited on the lower substrate 2, and then an amorphous silicon film is deposited on top of it. Subsequently, the amorphous silicon film is crystallized by means of a laser to form a polycrystalline silicon film, which is patterned, as shown in FIG. 2A, to form the active layer 44 of the thin film transistor TP and the active layer 14 of the switch device SW.
A gate insulating material 12a is deposited on the entire surface of the buffer film 4 with the active layers 14 and 44 thereon. Then, a photoresist is deposited on the entire surface of the gate insulating material 12a, and then is patterned, thereby forming a photoresist pattern 28 on the gate insulating material 12a. The gate insulating material 12a is patterned by a wet etching process using the photoresist pattern 28 as a mask, thereby forming the gate insulating film 12, as shown in FIG. 2C. At this moment, the gate insulating film 12 of the switch device SW is relatively thinner than the gate insulating film 12 of the thin film transistor TP.
A gate metal layer is deposited on the gate insulating film 12, and then is patterned, thereby forming the gate electrode 6 of the switch device SW and the gate electrode 36 of the thin film transistor TP, as shown in FIG. 2D.
The go-between insulating film 16 is deposited on the entire surface of the gate insulating film 12 provided with the gate electrodes 6 and 36, and then is patterned, thereby forming the source contact holes 20S and 50S and the drain contact holes 20D and 50D of the switch device SW and the thin film transistor TP penetrating the go-between insulating film 16 and the gate insulating film 12, as shown in FIG. 2E.
After this, a source/drain metal layer is deposited, and then is patterned, thereby forming the source electrodes 8 and 38 and the drain electrodes 10 and 40 of the switch devices SW and the thin film transistors TP, as shown in FIG. 2F. Herein, the source electrodes 8 and 38 and the drain electrodes 10 and 40 of the switch device SW and the thin film transistor TP are each connected to the active layers 14 and 44 through each of the source contact holes 20S and 50S, and the drain contact holes 20D and 50D, respectively.
The protective film 18 is deposited on the entire surface of the go-between insulating film 16 where the source electrodes 8 and 38 and the drain electrodes 10 and 40 of the switch device SW and the thin film transistor TP are formed, and then is patterned, thereby forming the pixel contact hole 24 to expose the drain electrode 40 of the thin film transistor TP, as shown in FIG. 2G.
A transparent conductive material is deposited on the protective film 18, and then is patterned, thereby forming the pixel electrode 22 connected to the drain electrode 40 of the thin film transistor TP through the pixel contact hole 24, as shown in FIG. 2H.
In this way, the polycrystalline LCD of the related art has a drive circuit like the multiplexor MUX formed on the lower substrate 2 together with the thin film transistor array included in the pixel display part 16. The gate insulating film 12 between the gate electrode 6 and the active layer 14 of the switch device included in the multiplexor is thinner than the gate insulating film 12 of the thin film transistor array. The capacitance of the capacitor formed between the active layer 14 and the gate electrode 6 with the gate insulating film 12 of the switch device SW therebetween is relatively higher than that of the thin film transistor array. The threshold voltage value of the switch device SW becomes relatively low in proportion to the capacitance of such a capacitor, so that the operation speed of the switch device can be improved.
However, there is difficulty in making the gate insulating film of the thin film transistor TP and the gate insulating film of the switch device SW uniform in their final thickness during the etching process for forming the gate insulating film 12, wherein the gate insulating film of the switch device SW is relatively thin and the gate insulating film of the thin film transistor TP is included in the picture display part.